1. Field
This patent document relates to a fuse cell circuit, a fuse cell array, and a memory device including the same.
2. Description of the Related Art
Fuses can be programmed by cutting them with lasers. The data held in a fuse array is stored based on whether the fuses have been cut. Thus, fuses can be programmed while they are in the wafer stage, but not after the wafers are mounted in a package.
In order to overcome this disadvantage, an e-fuse may be used. An e-fuse stores data by changing resistance states between the gate and the drain/source of a transistor.
FIG. 1 is a diagram illustrating an e-fuse that includes a transistor and operates as a resistor or a capacitor.
Referring to FIG. 1, the e-fuse includes a transistor T, which is configured to receive a power supply voltage through a gate G thereof and receive a ground voltage through a drain/source D/S thereof.
When a normal power supply voltage, which the transistor T can withstand, is applied to the gate G, the e-fuse operates as a capacitor C. Thus, no current flows between the gate G and the drain/source D/S. However, when a high power supply voltage, which the transistor T cannot withstand, is applied to the gate G, the gate G and the drain/source D/S may short-circuit as the gate oxide of the transistor T is destroyed. Then, the e-fuse operates as a resistor R. Thus, a current flows between the gate G and the drain/source D/S. Based on this phenomenon, the data stored in the e-fuse may be recognized by the amount of resistance present between the gate G and the drain/source D/S of the e-fuse. To recognize the data stored in an e-fuse, (1) the size of the transistor T may be increased to directly recognize the data without a separate sensing operation, or (2) an amplifier may be used to sense the current flowing in the transistor T without increasing the size of the transistor T. The two above-described methods are limited in terms of the area of an e-fuse, because the transistor T forming the e-fuse is large or there needs to be an amplifier for amplifying the data current.
FIG. 2 is a configuration diagram of a fuse cell array 200 including e-fuses.
Referring to FIG. 2, the fuse cell array 200 includes memory cells 201 to 232 arranged in a plurality of rows and columns (for example, eight rows and four columns in FIG. 2). The memory cells 201 to 232 include fuse transistors F1 to F32 and select transistors S1 to S32, respectively. The fuse transistors F1 to F32 are e-fuses which have the properties of a resistor or capacitor, depending on whether the e-fuses are ruptured. That is, the e-fuses F1 to F32 may act as resistive fuse transistors to store data based on the magnitude of resistance. The select transistors S1 to S32 electrically couple the fuse transistors F1 to F32 to column lines BL1 to BL4 under the control of row lines WLR1 to WLR8.
During a program operation, a selected row line is activated to turn on select transistors coupled thereto, and a high voltage applied to a selected program/read line. Furthermore, a low-level or high-level voltage is applied to a selected column line to program a selected fuse coupled thereto. When a low-level voltage is applied to the selected column line, the selected fuse ruptures.
During a read operation, a selected row line is activated to turn on select transistors coupled thereto, and a voltage suitable for the read operation is applied to a selected program/read line. Furthermore, a low-level voltage is applied to a selected column line to read data of a selected fuse coupled thereto. At this time, the data of the selected fuse may be recognized depending on whether current flows through the selected column line.
In FIG. 2, one terminal A of the fuse transistors F1 to F32 is isolated by an isolation layer (refer to 302 of FIG. 3) formed through an STI (Shallow Trench Isolation) process.
FIG. 3 is a cross-sectional view illustrating adjacent fuse cells 205 and 209 formed over a substrate.
Referring to FIG. 3, the fuse transistors F5 and F9 and the select transistors S5 and S9 may be formed over a semiconductor substrate 301. The transistors F5, F9, S5, and S9 may include active regions A1 to A5, gates G1 to G4, gate oxide layers OX1 to OX4 and the like.
In order to stably isolate the active regions A3 and A4, the isolation layer 302 may be formed between the active regions A3 and A4. Furthermore, a dummy gate DG may be formed over the isolation layer 302 to control the uniformity of the process. The existence of the isolation layer 302 may significantly increase the area consumed by the fuse cell array 200.